Timer triggered ADC at 8kHz

FreeRTOS Peripherals
1

I need to sample low quality (8ks/s) audio on the BW16 8720DN

I can get the examples using “ADC_TimerTrigCmd(3, 1, ENABLE);” working OK. The second parameter (1) is the number of milliseconds between triggers.

I made a copy of ADC_TimerTrigCmd() so that I could express the sample interval in microseconds, by changing the line:

TIM_InitStruct.TIM_Period = (PeriodMs *32768)/1000/2;//ms to tick

to read

TIM_InitStruct.TIM_Period = (PeriodMs *(32768/16))/(1000000/16)/2;//us to tick

I have divided top and bottom by 16 to avoid risk of overflow at the multiplication stage.

This works OK for 1000us (i.e. 1ms) but if I try to reduce it to 500 (i.e. 0.5ms) I see a crash:


Hard Fault Patch (Non-secure)
Enter CM BackTrace, SP 0x10042878


Firmware name: target_img2, hardware version: HW v1.0, software version: SW v1.0
Fault on thread TCP_IP

stact addr 0x10041980, size 0xf84, top 0x10042830
dump_stack sp point 0x10042898, task sp 0x10042830

===== Thread stack information =====
  addr: 10042830    data: 10041980
  addr: 10042834    data: ffffffbc
  addr: 10042838    data: 100418e0
  addr: 1004283c    data: 64
  addr: 10042840    data: 0
  addr: 10042844    data: 0
  addr: 10042848    data: 100428f4
  addr: 1004284c    data: 10020c38
  addr: 10042850    data: 100428f4
  addr: 10042854    data: 10012a55
  addr: 10042858    data: 0
  addr: 1004285c    data: 10042944
  addr: 10042860    data: 100418e0
  addr: 10042864    data: 64
  addr: 10042868    data: 1
  addr: 1004286c    data: 0
  addr: 10042870    data: 100418e0
  addr: 10042874    data: 1000d531
  addr: 10042878    data: e083cd8
  addr: 1004287c    data: 10028348
  addr: 10042880    data: 0
  addr: 10042884    data: 1002c448
  addr: 10042888    data: e01fe61
  addr: 1004288c    data: 10012a5d
  addr: 10042890    data: e001f32
  addr: 10042894    data: 21000000
  addr: 10042898    data: e083cd8
  addr: 1004289c    data: 10028348
  addr: 100428a0    data: e083cd8
  addr: 100428a4    data: 0
  addr: 100428a8    data: 10020c4c
  addr: 100428ac    data: 10020c44
  addr: 100428b0    data: 10020c44
  addr: 100428b4    data: 10012a5d
  addr: 100428b8    data: 10028348
  addr: 100428bc    data: 10012b3b
  addr: 100428c0    data: 10020c38
  addr: 100428c4    data: e083cd8
  addr: 100428c8    data: 0
  addr: 100428cc    data: 4040404
  addr: 100428d0    data: 10020c38
  addr: 100428d4    data: 6060606
  addr: 100428d8    data: 7070707
  addr: 100428dc    data: 8080808
  addr: 100428e0    data: 9090909
  addr: 100428e4    data: 10101010
  addr: 100428e8    data: 11111111
  addr: 100428ec    data: 10012749
  addr: 100428f0    data: 0
  addr: 100428f4    data: 0
  addr: 100428f8    data: 2020202
  addr: 100428fc    data: 1000cd8b
  addr: 10042900    data: a5a5a5a5
====================================
=================== Registers information ====================
  R0 : e083cd8
  R1 : 10028348
  R2 : 0
  R3 : 1002c448

  R12: e01fe61
  LR : 10012a5d
  PC : e001f32
  PSR: 21000000

==============================================================

stact addr 0x10041980, size 0xf84, top 0x10042830
Show more call stack info by run: addr2line -e target_img2.axf -f 0e001f32 10012a59 0e083cd4 0e083cd4 10012a59 10012b37 0e083cd4 10012745 1000cd87
Exit CM BackTrace

So far as I can see, the calculation would give a period (in ticks) of 8 (rounding) which I’d have expected to be OK.

(125us may be getting a little hairy with the timer period being just 2 - but we’re nowhere near that)

I note that the ADC can only be triggered by timers 0 to 3 which are all ‘slow’, i.e. with 32.768kHz clock, so no chance to use the high speed timers with a slightly less “hectic” period number.

Can anyone suggest a workaround?

2

Further testing shows that at 900us it is fine, but at 880us or below it crashes. Weird.