A hard fault is an exception that occurs because of an error during normal or exception processing. It often occurs during your software development. Upon facing a hard fault, there is still something that you could do to further analyze the error and troubleshoot the root cause of your bug.
In this article, I would like to share with you a tip that help you with solving the hard fault.
Introduction
Firstly, I would like to recommend Arm Cortex-M33 Devices Generic User Guide r0p4, which is a generic user guide for devices that implement the Arm Cortex-M33 processor. In this book, some information is described as implementation-defined, and some features are described as optional.
We would like to focus on Configurable Fault Status Register, the CFSR indicates the cause of a MemManage fault, BusFault, or UsageFault that explains the reason of different hard faults.
1. MemManage Fault Status Register MMFSR
The MMFSR is a subregister of the CFSR that takes the first 8 bits from bit0 to bit7 as indicated in the Figure above. The flags in the MMFSR indicate the cause of memory access faults. In an implementation with the Security Extension, this field is banked between Security states.
2. BusFault Status Register BFSR
The BFSR is a subregister of the CFSR that takes 8 bits from bit8 to bit 15 as indicated in the Figure above. The flags in the BFSR indicate the cause of a bus access fault.
3. UsageFault Status Register UFSR
The UFSR is a subregister of the CFSR that takes 16 bits chunks from bit 16 to bit 31 as indicated in the Figure above. The UFSR indicates the cause of a UsageFault. In an implementation with the Security Extension, this field is banked between Security states.
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By narrowing it down to the three sections of the fault status register in Configurable Fault Status Register, we could read more detailed reason caused for a certain hard fault. Since this is only an elementary level of instruction.
- For more information, you could read this article that provides you with more valuable tips and experiences: https://www.embedded.com/debugging-hard-faults-in-arm-cortex-m0-based-socs/.